1. Field of the Disclosure
The disclosure generally relates to a slurry composition with high planarity and a chemical mechanical polishing (CMP) process of a dielectric film using the same. More particularly, the disclosure relates to a high-planarity slurry composition comprising water, an abrasive, and an anionic polymeric carbon compound including a plurality of carboxyl groups, and a CMP process of a dielectric film using the same.
2. Description of the Related Technology
In fabrication of semiconductor devices, if planarity of each layer in the multi-lines is not good enough, it exerts adverse effects on the contact between the lines. As the width of circuit lines become thinner, it has become more difficult to obtain a plane wafer by a conventional etch-back or reflow process. Therefore, there has been a need for a new planarization process and a new wafer polishing process combining a mechanical process and a chemical process called chemical mechanical polishing (abbreviated as CMP), which was developed by IBM Company in the late 1980's. A deformed layer formed by a conventional mechanical polishing process can be a flaw on a semiconductor chip. In addition, although the deformed layer is not formed by a chemical polishing process, a flat pattern (i.e., pattern accuracy) cannot be achieved; instead, only a simple flat surface can be obtained. The basic concept of the CMP process is to polish a wafer by combining advantages of the above-described two processes.
As described above, the planarization process is necessarily required in fabrication of semiconductor devices, and such process includes resist etch back process, spin on glass (abbreviated as “SOG”) process, boro-phospho-silicate-glass (abbreviated as “BPSG”) reflow process, and CMP. Among them, CMP has been known to have a planarization range larger by 100 to 1,000 times those of other planarization processes.
A wafer is polished by a pad and slurry in the CMP process. However, the wafer is not completely planarized in the CMP process using conventional slurry. The degree of planarity (abbreviated as “DOP”) of the CMP process, which is generally defined by Equation 1 (below) cannot reach 1 through a removal of a step difference by the conventional CMP process. If a step difference still exists after the CMP process, a margin shortage of the depth of focus (abbreviated as “DOF”) in a subsequent exposure step and a margin shortage in an etching step induce a bridge formation or increase a leakage current, thereby causing the device to fail. Particularly, the margin shortage in a subsequent self-aligned contact (abbreviated as “SAC”) process affects the device fail when the wafer is not completely planarized in an inter layer dielectric (ILD) CMP process of a DRAM fabrication.
                              Degree          ⁢                                          ⁢          of          ⁢                                          ⁢          Planarity                =                  1          -                                    SH              f                                      SH              i                                                          [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, SHi is the abbreviation for initial step height, which represents a step difference before the CMP process, and SHf is the abbreviation for final step height, which represents another step difference after the CMP process. When the SHf is 0, then the DOP becomes 1, meaning complete planarization is achieved.
FIGS. 1a to 1c show the conventional CMP process. Pattern 1 is formed through a photo-etching process in the fabrication of a semiconductor device, and a region where the pattern is not formed is filled with an dielectric film 2 (see FIG. 1a). Herein, in order to remove step difference t1, a CMP process using abrasive 3 and pad 4 is conducted (see FIG. 1b). However, step difference t2 still remains after the CMP process was completed (see FIG. 1c).
When the step difference is removed by conventional CMP process, the degree of planarity cannot exceed 0.7 at its maximum due to various factors such as dielectric film deposition characteristics before the CMP process, degree of elasticity of the pad, characteristics of slurry and non-uniformity in the polishing process. In other words, the conventional method cannot decrease the step difference by more than 70% of the initial step height SHi and about 30% of the initial step height remains after the CMP process. As a result, it is difficult to apply the conventional method to a semiconductor device having fine circuit pattern, such as a device having a circuit line width of less than 100 nanometers (nm).